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From wiki.openlighting.org

The last version of the standard is called USITT DMX512-A and it is maintained by ESTA since 1998. In 2004 it was made an ANSI standard too, named 'E1.11, USITT DMX512-A' or 'ANSI E1.11-2004'. In 2008 it was revised [1] .

IF you are looking for info about connecting DMX equipment and setting addresses, look at this video tutorial from Martin.So far, the rest of this article is about technicalities.

DMX is characterized by its simplicity in how data are transferred from a controller to receiving equipment.

• 1Electrical

Electrical

DMX is based on the balanced serial connection standard EIA-485-A (a.k.a RS485).Only 5-pin XLR meets the standard (and products may meet the requirement by supplying adapters).Since the revision in 1998 the cables itself are not specified in DMX512-A (so it can be specified in separate standards?)In general the cable must fulfill the EIA-485 requirements of 120 Ohms (around 250 kHz) shielded twisted pair. One transmitter must be connected to maximum 32 receivers.

• Termination resistor tolerance is 120 Ohm +5 % / -10 % (108 – 126 Ohm).
• Each receiver must not load the differential line with more than 125 pF.

Use of category 5 UTP or STP

Other cable types have been examined to determine how well they are for DMX usage (as loose cables or in fixed building installations). The last report more or less concludes that for fixed installations, unshielded twisted pair in CAT 5 is good enough, even when it is mixed with 120 Ohm cable meant for EIA-485. The pulses from reflections and general degradation is not significant and harmless. See the three parts at http://www.esta.org/tsp/working_groups/CP/DMXoverCat5.htm .

See also this point in USITT's DMX faq:http://www.usitt.org/DMX512FAQ.aspx#a9(old link is [2]).

The cabling for DMX512-A should be described in the document called 'BSR E1.27-1 -- Portable Control Cables for Use with USITT DMX512/1990 and E1.11 [DMX512-A]'

The 8-position modular connector is allowed in the DMX512-A as an alternate connector if there is not space enough for XLR5 or for fixed installations in 'controlled access areas'.Pin-out:

Both common wires are mandatory, and must have same potential in equipment sockets.

Voltages and power dissipation

The power dissipation in the 120 Ohm terminating resistors depends on the differential voltage between the two data wires.If the transmitter only makes a 5 V differential voltage (which is common), the power dissipation is P= U*U/R= 5*5/120 = 208 mW.

According to [3] and the DMX512-A standard, the maximum absolute differential voltage allowed by the EIA485 standard is 6 V.This gives the maximum power dissipation is P= U*U/R= 6*6/120 = 300 mW. So it is best to use 1/2 W resistors, to keep them cool enough not to damage itself or weakening the solderings.

Transceiver chips made for 5 V (they seem to be widely used):

Transmitter/receiver topologies

To avoid ground loops between equipment and improve reception performance, the transmitters and receivers for the DMX line must use a good combination of transmitter/receiver topologies. Some are not allowed, some are accepted with warning labels and some are preferred. See http://www.usitt.org/standards/DMX512_FAQ.html#FAQ_15 .

Transmitters should use 'earth ground' as a reference for the positive/negative voltages that is put on the two data lines.Receivers should be 'isolated'.

The protocol

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A Universe contains 512 addresses and a single DMX line (cable) can only transmit one universe. I.e. a controller with two universes need two DMX lines (daisy chains including splitters). A universe is normally thought of as an address space (in the controller), the cables that transmits it and the equipment that receives it.

• The DMX signal is made up of a sequence - called a packet - which is sent over and over again (to increase robustness).
• It is up to the controller/transmitter to decide how many of the 512 values is sent. A shorter packet means faster cycles.
• A receiver must be set or programmed to an address it listens to. If a receiver listens to multiple addresses, the set one is the first. (It depends on implementation.)
• Multiple receiver can listen to the same address - the DMX system does not care.

A packet has the following sequence:

• Break
• Mark After Break (MAB)
• The 'start code' frame (Sometimes called address 0) Alternate start codes
• 1-512 slots/frames with the values of the channels. The first value is for address '1', the next for address 2 etc.

(Note: A packet must have a minimum length in time)

• A slot/frame contains the value for one address, has one start bit and two stop bits.
• The address number is not sent over the lines, so the receiver must count the received slots from the start of the sequence to find the wanted value.
• The start code is used to alter the meaning of the data bytes in the rest of the packet. The default is 0, and the remaining 255 values is rarely used (by definition 0 means dimmers, but is used for intelligent light as well).

Note that some people and texts use the words frame and packet in the opposite sense than stated here.

Timings

The clock rate is 250 kHz so each symbol bit on the wire is 4 microseconds long (period time).

Symbol length is 4 +/- 0.08us for 245 - 255 k baud/s, with non-return-zero between symbol bits. To transmit 8 data bits it take 11 symbols because the use of one start bit and two stop bits around each data byte. Slot/address number is known by counting slots from the long packet break in the beginning of each packet.

The maximum packet rate is 44 updates/s if all 513 slots are transmitted (start code + 512 values), but can be higher if fewer slots are transmitted. If only packets only consists of a start code + 24 values, up to 830 updates/s can be made.

The Rx req. column shows what a receiver must be able to handle of valid timings.

Note that the minimum length of 'Mark after break' was doubled from 4 to 8 us in 1990, and receivers can be backward compatible by accepting the shortest time.

The slot time must be precise, or else the receiver should discard the whole packet, e.g. if the second stop bit is missing.

There must be at least one packet with start code=0 per second, and a receiving product must specify what happens when this time is exceeded.

Here is a nice overview of the different parts of a DMX packet with timings etc.: http://www.erwinrol.com/index.php?stagecraft/dmx.php.These timing values matches the ones in the DMX standard from 2004.

Idle must be high level (mark level, 'Mark before break').

As a receiver must handle varying 'mark time between slots', it needs to synchronize to each start bit in each slot.

Sources and additional reading

• Thorough DMX description and a long list of good references to other sites and projects. Much better than a Google search!

• ePanorama (thorough descriptions of most details, lots of links)

• Ujjal's DMX512 Pages (down-to-earth walk-through, also a good historical overview from before DMX )
• The anatomy of DMX512 (a nice, short overview)

• History from mechanical dimming over analog lines, multiplexing, DMX and to ACN in three pages.

See also

In the fields of digital electronics and computer hardware, multi-channel memory architecture is a technology that increases the data transfer rate between the DRAM memory and the memory controller by adding more channels of communication between them. Theoretically this multiplies the data rate by exactly the number of channels present. Dual-channel memory employs two channels. The technique goes back as far as the 1960s having been used in IBM System/360 Model 91 and in CDC 6600.^[1]

Modern high-end processors like the IntelCore i9 and AMDRyzen Threadripper series, along with various Intel Xeons support quad-channel memory. In March 2010, AMD released Socket G34 and Magny-Cours Opteron 6100 series^[2] processors with support for quad-channel memory. In 2006, Intel released chipsets that support quad-channel memory for its LGA771 platform^[3] and later in 2011 for its LGA2011 platform.^[4] Microcomputer chipsets with even more channels were designed; for example, the chipset in the AlphaStation 600 (1995) supports eight-channel memory, but the backplane of the machine limited operation to four channels.^[5]

Dual-channel architecture[edit]

Dual-channel-enabled memory controllers in a PC system architecture use two 64-bit data channels. Dual-channel should not be confused with double data rate (DDR), in which data exchange happens twice per DRAM clock. The two technologies are independent of each other, and many motherboards use both by using DDR memory in a dual-channel configuration.

Operation[edit]

Dual-channel architecture requires a dual-channel-capable motherboard and two or more DDR, DDR2, DDR3, DDR4, or DDR5 memory modules. The memory modules are installed into matching banks, each of which belongs to a different channel. The motherboard's manual will provide an explanation of how to install memory for that particular unit. A matched pair of memory modules may usually be placed in the first bank of each channel, and a different-capacity pair of modules in the second bank.^[6] Modules rated at different speeds can be run in dual-channel mode, although the motherboard will then run all memory modules at the speed of the slowest module. Some motherboards, however, have compatibility issues with certain brands or models of memory when attempting to use them in dual-channel mode. For this reason, it is generally advised to use identical pairs of memory modules, which is why most memory manufacturers now sell 'kits' of matched-pair DIMMs. Several motherboard manufacturers only support configurations where a 'matched pair' of modules are used. A matching pair needs to match in:

• Capacity (e.g. 1024 MB). Certain Intel chipsets support different capacity chips in what they call Flex Mode: the capacity that can be matched is run in dual-channel, while the remainder runs in single-channel.
• Speed (e.g. PC5300). If speed is not the same, the lower speed of the two modules will be used. Likewise, the higher latency of the two modules will be used.
• Same CAS Latency (CL) or Column Address Strobe.
• Number of chips and sides (e.g. two sides with four chips on each side).
• Matching size of rows and columns.

Dual-channel architecture is a technology implemented on motherboards by the motherboard manufacturer and does not apply to memory modules. Theoretically any matched pair of memory modules may be used in either single- or dual-channel operation, provided the motherboard supports this architecture.

Performance[edit]

Theoretically, dual-channel configurations double the memory bandwidth when compared to single-channel configurations. This should not be confused with double data rate (DDR) memory, which doubles the usage of DRAM bus by transferring data both on the rising and falling edges of the memory bus clock signals.

A benchmark performed by TweakTown, using SiSoftware Sandra, measured around 70% increase in performance of a quadruple-channel configuration, when compared to a dual-channel configuration.^{[7]:p. 5} Other tests performed by TweakTown on the same subject showed no significant differences in performance, leading to a conclusion that not all benchmark software is up to the task of exploiting increased parallelism offered by the multi-channel memory configurations.^{[7]:p. 6}

Ganged versus unganged[edit]

Dual-channel was originally conceived as a way to maximize memory throughput by combining two 64-bit buses into a single 128-bit bus.^{[disputed][citation needed]} This is retrospectively called the 'ganged' mode. However, due to lackluster performance gains in consumer applications,^[8] more modern implementations of dual-channel use the 'unganged' mode by default, which maintains two 64-bit memory buses but allows independent access to each channel, in support of multithreading with multi-core processors.^[9][10]

'Ganged' versus 'unganged' difference could also be envisioned as an analogy with the way RAID 0 works, when compared to JBOD.^[11] With RAID 0 (which is analogous to 'ganged' mode), it is up to the additional logic layer to provide better (ideally even) usage of all available hardware units (storage devices, or memory modules) and increased overall performance. On the other hand, with JBOD (which is analogous to 'unganged' mode) it is relied on the statistical usage patterns to ensure increased overall performance through even usage of all available hardware units.^[9][10]

Triple-channel architecture[edit]

Operation[edit]

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DDR3 triple-channel architecture is used in the IntelCore i7-900 series (the Intel Core i7-800 series only support up to dual-channel). The LGA 1366 platform (e.g. Intel X58) supports DDR3 triple-channel, normally 1333 and 1600Mhz, but can run at higher clock speeds on certain motherboards. AMD Socket AM3 processors do not use the DDR3 triple-channel architecture but instead use dual-channel DDR3 memory. The same applies to the Intel Core i3, Core i5 and Core i7-800 series, which are used on the LGA 1156 platforms (e.g., Intel P55). According to Intel, a Core i7 with DDR3 operating at 1066 MHz will offer peak data transfer rates of 25.6 GB/s when operating in triple-channel interleaved mode. This, Intel claims, leads to faster system performance as well as higher performance per watt.^[12]

When operating in triple-channel mode, memory latency is reduced due to interleaving, meaning that each module is accessed sequentially for smaller bits of data rather than completely filling up one module before accessing the next one. Data is spread amongst the modules in an alternating pattern, potentially tripling available memory bandwidth for the same amount of data, as opposed to storing it all on one module.

The architecture can only be used when all three, or a multiple of three, memory modules are identical in capacity and speed, and are placed in three-channel slots. When two memory modules are installed, the architecture will operate in dual-channel architecture mode.^[13]

Supporting processors[edit]

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Quad-channel architecture[edit]

Operation[edit]

Quad-channel DDR4 has replaced DDR3 on the Intel X99LGA 2011 platform, and is also used in AMD's Threadripper platform.^[16]DDR3 quad-channel architecture is used in the AMDG34 platform and in the Intel X79LGA 2011 platform. AMD processors for the C32 platform and Intel processors for the LGA 1155 platform (e.g., Intel Z68) use dual-channel DDR3 memory instead.

The architecture can be used only when all four memory modules (or a multiple of four) are identical in capacity and speed, and are placed in quad-channel slots. When two memory modules are installed, the architecture will operate in a dual-channel mode; when three memory modules are installed, the architecture will operate in a triple-channel mode.^[13]

Supporting processors[edit]

Six-channel architecture[edit]

Supported by Qualcomm Centriq server processors,^[19] and Intel Xeon Scalable processors.^[20]

Eight-channel architecture[edit]

Supported by AMD Epyc and Cavium ThunderX2 server processors.^[21][22]

See also[edit]

References[edit]

1. ^Jacob, Bruce; Ng, Spencer; Wang, David (2007). Memory systems: cache, DRAM, disk. Morgan Kaufmann. p. 318. ISBN978-0-12-379751-3.
2. ^ ^ab'Opteron 6000 Series Platform Quick Reference Guide'(PDF). AMD. Archived from the original(PDF) on 2012-05-12. Retrieved 2012-10-15.
3. ^5000P memory controller, Intel.
4. ^Intel LGA2011 socket x68 express chipset pictured, Tech power up.
5. ^John H. Zurawski; John E. Murray; Paul J. Lemmon, 'The Design and Verification of the AlphaStation 600 5-series Workstation', HP, 7 (1).
6. ^'Intel Dual-Channel DDR Memory Architecture White Paper'(PDF) (Rev. 1.0 ed.). Infineon Technologies North America and Kingston Technology. September 2003. Archived from the original(PDF, 1021 KB) on 2011-09-29. Retrieved 2007-09-06.
7. ^ ^abShawn Baker (2011-11-16). 'Intel X79 Quad Channel and Z68 Dual Channel Memory Performance Analysis'. TweakTown. Retrieved 2013-11-30.
8. ^'AMD Phenom X4 Memory Controller in the Ganged/ Unganged Mode'. ixbtlabs.com. 2008-08-16. Retrieved 2014-01-09.
9. ^ ^abGionatan Danti (2010-06-17). 'The Phenom / PhenomII memory controller: ganged vs unganged mode benchmarked'. ilsistemista.net. Retrieved 2014-01-09.
10. ^ ^ab'BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors'(PDF). amd.com. 2013-01-11. pp. 107–108. Retrieved 2014-01-09. When the DCTs are in ganged mode, as specified by [The DRAM Controller Select Low Register] F2x110 [DctGangEn], then each logical DIMM is two channels wide. Each physical DIMM of a 2-channel logical DIMM is required to be the same size and use the same timing parameters. Both DCTs must be programmed with the same information (see 2.8.1 [DCT Configuration Registers]). When the DCTs are in unganged mode, a logical DIMM is equivalent to a 64-bit physical DIMM and each channel is controlled by a different DCT. Typical systems are recommended to run in unganged mode to benefit from the additional parallelism generated by using the DCTs independently. See 2.12.2 [DRAM Considerations for ECC] for DRAM ECC implications of ganged and unganged mode. Ganged mode is not supported for S1g3, S1g4, ASB2, and G34 processors.
11. ^Rouse, Margaret (September 2005). 'JBOD (just a bunch of disks or just a bunch of drives)'. SearchStorage.TechTarget.com. Retrieved 2014-01-09.
12. ^X58 Product Brief(PDF), Intel
13. ^ ^abDesktop Boards – Triple Memory Modules, Intel, Single- and Multichannel Memory Modes
14. ^'Core i7 Family Product Comparison'. Intel. Memory Specifications: # of Memory Channels.
15. ^'Xeon Family Product Comparison'. Intel. Memory Specifications: # of Memory Channels.
16. ^AMD Ryzen Threadripper And Vega Attack Prey At 4K, Quad GPUs Shred Blender, Radeon RX Vega Hits In July, '....with 16 cores and 32 threads with support for quad-channel DDR4 memory......'
17. ^'AMD Opteron 6200 Series Processor Quick Reference Guide'(PDF). Retrieved 2012-10-15.
18. ^'AMD Opteron 6300 Series processor Quick Reference Guide'(PDF). Retrieved 2013-12-11.
19. ^Kennedy, Patrick (23 August 2017). 'Qualcomm Centriq 2400 ARM CPU from Hot Chips 29'. Serve The Home. Retrieved 14 November 2017.
20. ^https://www.intel.in/content/www/in/en/products/processors/xeon/scalable/bronze-processors/bronze-3106.html
21. ^Cutress, Ian (7 March 2017). 'AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2'. Anandtech. Retrieved 7 March 2017.
22. ^Kennedy, Patrick (9 November 2017). 'Cavium ThunderX2 and OCP Platform Details'. Serve the Home. Retrieved 14 November 2017.

External links[edit]

• 'Single, dual, triple and flex memory modes', Desktop motherboards support, Intel.
• Everything You Need to Know About the Dual-, Triple-, and Quad-Channel Memory Architectures, November 2011, Hardware Secrets
• Memory Configuration Guide for X9 Series DP Motherboards – Revised Ivy Bridge Update (Socket R & B2), January 2014, Super Micro Computer, Inc.
• DDR3 Memory Frequency Guide, May 2012, AMD (archived)